HDL-SCHEM-Editor for VHDL and Verilog

Features:

• HDL-SCHEM-Editor can draw a hierarchical schematic.
• HDL-SCHEM-Editor can instantiate an already existing HDL module as a symbol in the schematic.
• HDL-SCHEM-Editor can instantiate an already existing HDL-SCHEM-Editor design as a symbol in the schematic.
• HDL-SCHEM-Editor can instantiate an already existing HDL-FSM-Editor design (see: HDL-FSM-Editor) as a symbol in the schematic.
• HDL-SCHEM-Editor can automatically add wires to all the ports of a symbol.
• HDL-SCHEM-Editor can add glue logic to the schematic.
• HDL-SCHEM-Editor can copy and paste.
• HDL-SCHEM-Editor can generate HDL-code (VHDL, Verilog, SystemVerilog) from the schematic.
• HDL-SCHEM-Editor can link the generated HDL-code from the "Generated HDL"-Tab to the schematic.
• HDL-SCHEM-Editor can link the compiler messages in the "Compile Messages"-Tab to the schematic or to the "Generated HDL"-Tab.
• HDL-SCHEM-Editor can generate a list which contains all HDL filenames which are needed for the schematic (together with library information).
• HDL-SCHEM-Editor can compile a flat and also a hierarchical design by a user-specified compile command.
• HDL-SCHEM-Editor is the most simple Schematic-Editor: It is very easy to use and avoids unnecessary functional overload.
• HDL-SCHEM-Editor is platform independent, it runs at any platform which supports Python3.
• HDL-SCHEM-Editor is freeware and open source.

Advantages:

• When using HDL-SCHEM-Editor you create HDL designs several times faster compared to writing them manually in a text editor.
• When using HDL-SCHEM-Editor you implement less mistakes, as the schematic provides a clear overview of the functionality of the design.
• When using HDL-SCHEM-Editor the dataflow through your design gets visible.
• When using HDL-SCHEM-Editor testbenches are created by some mouse clicks.
• When using HDL-SCHEM-Editor your colleagues can easily read, understand and modify the design you originally provided.
• When using HDL-SCHEM-Editor you will have immediate access to the generated HDL code inside HDL-SCHEM-Editor without using another tool.

Prerequisites:

• You should be familiar with a hardware description language such as VHDL or Verilog, as you will have to write some declarations, signal definitions and glue logic by yourself using the selected HDL.
• You should have an HDL-compiler and an HDL-simulator for the verification of your implemented design.

Commandline parameters:

• Filename:

  HDL-SCHEM-Editor will load the file, if it is a HDL-SCHEM-Editor design.

• -no_version_check:

  HDL-SCHEM-Editor will not access the internet to check for a newer version.

• -no_message:

  HDL-SCHEM-Editor will not show the message with actual news from HDL-SCHEM-Editor.

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Control-Tab:

Here you define several items which control the generation of the HDL-design:

• Module name:

  The module name be used inside the generated HDL and for the filenames of the generated files.

• Language:

  Here you can select between VHDL, Verilog, System-Verilog. The selected language determines which language has to be used for all the manually entered HDL and which language will be used at HDL generation.

• Path for generated HDL:

  In this folder you will find the generated HDL-file(s).

• Number of files:

  This is only relevant for VHDL designs, where entity and architecture can be stored in different files.

• Compile command for single module:

  If your schematic does not have hierarchy:
  Specify a semicolon separated list of system commands which runs your HDL-compiler/simulator on the generated HDL-code.
  HDL-SCHEM-Editor will run the commands whenever you start a compile for a single module from HDL-SCHEM-Editor.
  If your VHDL schematic needs a non-standard package, specify a compile command for this package in the first place of the compile command list.

• Compile through hierarchy command:

  If your schematic has hierarchy: In this case several HDL files must be compiled in the correct order. HDL-SCHEM-Editor supports you by creating the file hdl-file-list.txt. This file contains all the needed HDL filenames and library-informations. Your script, which compiles all the HDL-files, can read this file and create and execute all the needed compile commands. You can put the name of your script into this field and HDL-SCHEM-Editor will run the script whenever you start a compile from HDL-SCHEM-Editor.

• Edit command:

  Here you specify a system command which runs your favoured editor (started by Ctrl+e) when editing any text box.

• HDL-FSM-Editor command:

  Here you specify a system command which runs HDL-FSM-Editor. This command is needed when a symbol, representing a HDL-FSM-Editor design,
  shall be opened by a double click with the left mouse button.

• Symbolic library name for the module:

  When a HDL-SCHEM-Editor design is inserted as a instance into another HDL-SCHEM-Editor design,
  then this libary name is copied into the instance properties (see Instance Properties Dialog below).
  This library name is used, when a hdl-file-list is generated. It defines, in which libary the module shall be compiled. See chapter Hierarchical designs and hdl-file-list.
  When no library name is specified, "work" is used.

• Additional sources for the module:

  This field can contain a comma separated list of file-names.
  The file-names are used, when a hdl-file-list is created. See chapter Hierarchical designs and hdl-file-list.
  The file-names are copied into the hdl-file-list, which will be generated at a hierarchical compile.
  The files can contain packages, which are used by the module.
  The files can contain other hdl-file-lists, which are needed for the compilation of the module.

• Working directory:

  When the compile commands run they create some files. These files are stored in the working directory.

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Entity-declarations-Tab (VHDL) / Parameters-Tab (Verilog):

• When you have selected VHDL:

  There is a dedicated text entry field for package- and generic-declarations.

• When you have selected Verilog:

  There is a dedicated text entry field for parameter-declarations.

• When you have selected System-Verilog:

  There is a dedicated text entry field for parameter-declarations.

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Architecture-Declarations-Tab (VHDL)/Internal Declarations-Tab (Verilog):

• When you have selected VHDL:

  There is a text entry field for package-, architecture(first)- and architecture(last)- declarations.

• When you have selected Verilog:

  There is a text entry field for internal declarations.

• When you have selected System-Verilog:

  There is a text entry field for internal declarations.

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Diagram-Tab:

The schematic is drawn in this tab and a hidable hierarchical view is available (from which designs can be opened by doubleclick).
Each graphical element can be moved by picking it with the left mouse button.
Each graphical element can be deleted by moving the mouse pointer over the element and pressing the "Delete" key.
For VHDL designs several alternative schematics can be entered by using the "new Architecture" button (which architecture is used is controlled by the instance).
The following graphical elements are available:

• Input/Output/Inout port:

  A new port is inserted by clicking the "new Input"/"new Output"/"new Inout" button and placing the connector into the diagram by the left mouse button.
  "Escape" aborts inserting the new connector.
  The port gets its name and type from the wire, which is connected to the connector.
  The connector can be rotated by 90 degree steps with a double left mouse click.

• Wire/Bus:

  A new wire/bus is inserted by clicking the "new Wire"/"new Bus" button.
  Afterwards the first left mouse button click determines the start point of the wire/bus in the diagram.
  Each next single left mouse click inserts an edge for the wire/bus.
  A double left mouse click determines the end point of the wire/bus.
  "Escape" aborts inserting a new wire/bus.
  The right mouse button over a wire/bus opens a menu for highlighting of wire/bus.
  By pressing Shift and right-mouse-button several times at a wire/bus, an arrowhead is added to the start or the end of the wire/bus.
  Wires/busses can be moved by picking them with the left mouse button.
  Several open wire/bus end points can be moved together by connecting a new block (see below) to all of them and then by moving the block (which can be deleted afterwards).
  If a not connected wire/bus without any edge is picked in the middle, then the complete wire/bus is moved.
  If a not connected wire/bus end point is picked, then only the end point is moved.
  A connected wire/bus end point (connected to a connector/instance-pin/block/wire/bus) can only be moved, when the "Shift" key is pressed at the mouse click.
  If a wire/bus end point is placed at another wire, then the two wires are connected and get the same signal name.
  If a signal definition describes a single signal, a thin line is shown in the diagram.
  If a signal definition describes an array of signals, a thick line is shown in the diagram.

• Signal Name:

  Each wire/bus gets a default signal definition, from which only the signal name is displayed.
  The signal definition is built with the HDL language which is defined in the Control-tab.
  The signal definition can be changed by a double left mouse button click into the signal name.
  A triple mouse click into a signal name positions the insert cursor at the signal name character under the mouse pointer.
  "Return" stores the changes of the signal definition.
  "Return"+"Control" stores the changes of the signal definition not only to the wire/bus under work, but to all wires/busses which have the same signal name.
  "Escape" aborts editing the signal definition.
  The signal definition must not contain any semicolon.
  The signal definition may contain a comment at the end of the line.
  The signal definition may contain an initialization, if VHDL is used.
  The signal definition may contain a sub range, if it defines a bus.
  Example of a signal definition of a wire where the signal has 8 bits, but the wire only uses bits 7:4:
  VHDL: data_bus(7 downto 4) : std_logic_vector(31 downto 0) := X"12345678" -- comment
  Verilog: reg [31:0] data_bus : [7:4] // comment

• Block:

  A new block is inserted by clicking the "new Block" button.
  Afterwards the block can be placed into the diagram by a left mouse button click.
  "Escape" aborts inserting a new block.
  A block contains the glue logic, which may be needed additionally between the instances of the design.
  The size of a block can be changed by moving its corners with the left mouse button.
  A block can be edited by a double left mouse button click or by "Ctrl-e" when the mouse pointer is over the block.
  "Ctrl-e" executes the command which is provided in the Control-tab.
  When the block is edited by a double left mouse button click, then the changes have to be stored by "Ctrl-s" or rejected by "Escape".
  When the block is edited by "Ctrl-e" then the commands of the started editor have to be used to store the changes.
  The temporary file which is used in this case will be removed after the changes were copied into the block.
  After editing the HDL code of the block the size of the block can be adapted.
  This is done by picking one of the four edges of the block with the left mouse button.
  A block can be moved by picking it at any side with the left mouse button, but if the mouse pointer is too far inside the block, moving will not work.
  Any wire/bus can be connected to any side of a block (not needed, can be used to show the signal flow).
  By putting a comment starting with an integer at the top of the block code, the position of the block code in the HDL can be defined.
  The object with the smallest number is located at the first position in the HDL.
  Comments which only contain such an integer are not placed into the HDL code.
  If the mouse pointer is over the instance/module name for a second, a small window pops up, showing the names with a bigger font.

• Instance:

  A new instance is inserted by clicking the "new Instance" button.
  This opens a file selection dialog were a file can be chosen, which contains a description of a module.
  HDL-SCHEM-Editor can handle HDL-SCHEM-Editor-, HDL-FSM-Editor- (see HDL-FSM-Editor), VHDL-, Verilog- and System-Verilog-files.
  After reading the file a symbol for the module is created, which can be placed with a left mouse button click into the diagram.
  "Escape" aborts inserting a new instance.
  The size of an instance can be changed by moving its corners with the left mouse button.
  At mixed designs (VHDL and Verilog) HDL-SCHEM-Editor only supports generics(VHDL)/parameters(Verilog) of type integer.
  An instance can be edited by a double left mouse button click when the mouse pointer is over the block:
  - If the instance is a HDL-SCHEM-Editor design, then a new HDL-SCHEM-Editor-window opens.
  - If the instance is a HDL-FSM-Editor design, then a HDL-FSM-Editor-window opens.
  - In all other cases the text editor command provided in the Control-tab is used to show the content of the instance.
  The instance name can be modified by a double left mouse button click, the changes are stored by "Return" or dismissed by "Escape".
  The generic map (VHDL) or parameter list (Verilog) can be edited by a double left mouse button click, the changes are stored by "Ctrl-s" or dismissed by "Escape".
  By putting a comment starting with an integer at the end of the instance name, the position of the instance in the HDL can be defined.
  The object with the smallest number is located at the first position in the HDL.
  Comments which only contain such an integer are not copied into the HDL code.

• Generate:

  A new generate is inserted by clicking the "new Generate" button.
  By drawing a rectangle with the mouse a region of the schematic can be enclosed into the generate.
  The generate condition must be defined and will appear in the HDL.
  For VHDL the syntax is "<label:> if <condition> generate", "<label:> for <parameter> in <start> to/downto <end> generate"
  For Verilog the syntax without label is "generate if (<condition>)", "for (<parameter>=start-value; <parameter>=end-value; <parameter>=<parameter>+delta)"
  For Verilog the syntax with label is "generate if (<condition>)" begin : <label>, "for (<parameter>=start-value; <parameter>=end-value; <parameter>=<parameter>+delta) begin : <label>"
  By putting a comment starting with an integer at the end of the generate condition, the position of the generate in the HDL can be defined.
  The object with the smallest number is located at the first position in the HDL.
  Comments which only contain such an integer are not placed into the HDL code.

Configure and manipulate the graphical elements:

• Instance Actions Menu:

  The instance actions menu is opened by a click with the right mouse button when the mouse pointer is over the instance.
  The menu has these entries:

  • Open source:

    Opens a new window with the source of the instance. This can also be done by a doubleclick at the symbol.

  • Update symbol from source (with generics):

    The source file of the instance is read again and the ports, generic map (VHDL), parameter list (Verilog) and module name and architecture name are updated.
    The generic map and the parameter list use the default values defined in the source file.

  • Update symbol from source (without generics):

    The source file of the instance is read again and the ports and module name and architecture name are updated.
    The generic map and the parameter list are not updated.

  • Add input and output connectors:

    At each port of the module a wire and a connector is added. The port name and the port type is used as signal name and signal type without any change.

  • Add signal stubs and keep suffixes ("_i", "_o", "_io"):

    At each port of the module a wire is added. The port name and the port type is used as signal name and signal type without any change.
    Often "_i", "_o", "_io" are used to identify names as port-names.
    If all the ports of the symbol will be used as ports of the design, then all the suffixes should be kept.

  • Add signal stubs and remove suffixes ("_i", "_o", "_io"):

    At each port of the module a wire is added. If any port name ends with "_i", "_o", "_io" then this suffix is not used for the signal name.
    Often "_i", "_o", "_io" are used to identify names as port-names.
    If all the ports of the symbol will be used as signals in the design, then all the suffixes should be removed.

  • Add signal stubs and ask at each suffix ("_i", "_o", "_io"):

    At each port of the module a wire is added. If any port name ends with "_i", "_o", "_io" then a dialog window pops up and asks if the suffix should be removed.
    This can be used when not all ports of the symbol which have a suffix are used as a port of the design.

  • Edit properties:

    This menu entry opens the instance properties dialog. Several properties of the symbol can be defined there.
    See chapter Instance Properties Dialog below.

  • Hide/Show ranges:

    The range of the ports of the instance can be hidden or shown by this menu entry.

• Instance Properties Dialog:

  If the symbol represents a VHDL module:

  • A VHDL library name can be specified, which is used when a configuration statement shall be placed inside the generated VHDL.
  • If "Embedded" configuration is selected for a instance then in the generated VHDL a configuration (which will use a specified architecture name) is
    added to the architecture declarative section or to the declaration section of a surrounding generate.
  • If "At Instance" is selected then the configuration is added to the module instance declaration in the generated VHDL.
    In this case also the architecture name specified in "VHDL Architecture Name" is used and
    in this case no component declaration is generated for the VHDL.
  • The architecture name is filled in when the symbol is instantiated first.
    If the instance is read from a VHDL file and the architecture name is found, this name is used.
    If the instance is a HDL-SCHEM-Editor VHDL design with one architecture, its name is used.
    If the instance is a HDL-SCHEM-Editor VHDL design which has more than one architecture,
    all the architecture names are listed in the combobox and can be chosen.
    The architecture name is used for:
    - Configuration statements (embedded or at instance) in the generated VHDL
    - Reading in the correct architecture from a HDL-SCHEM-Editor VHDL design, when creating the hdl-file-list for hierarchical compile.
    - Reading in the correct architecture from a HDL-SCHEM-Editor VHDL design, when signals are highlighted through hierarchy.
    - Opening the correct architecture from a HDL-SCHEM-Editor VHDL design, when the symbol is double clicked.
    

  If the symbol represents a Verilog module:

  • Then only a Verilog library name can be specified. But (in contrary to VHDL) Verilog has no "configuration" concept.
    So the library name is only used when a hdl-file-list is generated. See chapter Hierarchical designs and hdl-file-list.

  The "Source File-Name" field contains the filename which was selected when the symbol was inserted into the schematic.
  This file-name can be changed here and when "Store" is pressed the symbol will get updated.
  A second file-name (separated by ',') can be entered here, if the first file only contains the entity.
  This second file must then contain the VHDL-architecture and is only needed as entry in the hdl-file-list.

  The content of the field "Additional Sources is only used, when a hdl-file-list is generated. See chapter Hierarchical designs and hdl-file-list.
  When the symbol is a HDL-SCHEM-Editor design, the field is filled automatically, when the instance is created.

  When the port of a symbol is an array, then by default the range of the array is visible at the symbol. By selecting "Hide" the range will get invisible.

• Selection:

  A selection can be created by drawing a rectangle with the left mouse button pressed down.
  Only objects which are completely captured by the rectangle get selected and turn their color into red.
  An exception to this rule are the ports of an instance: They belong to the symbol object but can be selected separetely.
  A selection can be moved by picking it with the left mouse button.
  A selection can be deleted by pressing the delete key (exception: instance ports cannot be deleted).
  A selection can be copied into a paste buffer by "Ctrl-c" or by pressing the "Copy Selection" button (exception: instance ports cannot be copied).
  The content of the paste buffer can be inserted into the diagram by "Ctrl-v" or by pressing the "Paste" button.

• Hierarchical designs and hdl-file-list:

  HDL-SCHEM-Editor can compile a flat design or a hierarchical design.
  For both cases a command has to be specified in the Control-Tab:

  • A flat design is easy to handle most of the time:
    The HDL can be stored in 1 file, so that only 1 file has to be compiled and the compile command can easily be specified.
    But even for a flat design sometimes several files have to be compiled,
    because the HDL may be divided into 2 files or because packages are used (only at VHDL).
    So several commands are needed and can be inserted as a list (separated by semicolons) into the compile command field.
  • At hierarchical designs it gets more complicated:
    There are much more files involved and the compile order is sometimes complicated to determine.
    In case of VHDL the designs have to be compiled into the correctly named libraries.
    Even at Verilog designs there might be not only one library but several libraries.
    Therefore it is better not to insert many commands into the hierarchical compile command field,
    but to insert only the name of a script which creates and executes all the needed compile commands.
    But then at any change of the hierarchy this script has to be updated (if it not reads the hdl-file-list created by HDL-SCHEM-Editor).

  So often a file is needed which contains all source files in the compile order and additionally contains library information.
  HDL-SCHEM-Editor supports this by creating the file "hdl_file_list_<module-name.txt>" when "Compile through Hierarchy" is
  started ("Compile through Hierarchy" can also be used for flat designs).
  The created hdl-file-list can then be read by the hierarchical compile script (see Control-tab, field "Compile through hierarchy command")
  and so the compile script can create and execute compile commands of right order and with right parameters.

  There are several places where information is stored, which is needed for the generation of the hdl-file-list:

  • Control-tab, field "Symbolic library for the module".
  • Instance properties dialog, field "VHDL library name" (only for VHDL instance).
  • Instance properties dialog, field "Verilog library name" (only for Verilog instance).
  • Instance properties dialog, field "Additional sources":
    The "Additional sources" field can have:
    One entry: This must be the name of a hdl-file-list for this instance. The name is copied into the hdl-file-list which is created by HDL-SCHEM-Editor.
    Several entries: This must be a complete, comma separated file list in compile order for this instance. All entries are copied into the hdl-file-list which is created by HDL-SCHEM-Editor.

Editing actions:

• Using the right mouse button you can define a rectangle which adapts the visible area in the editor window.
• Using "view all" shows the complete diagram in the editor window.
• Using "view last" shows the last visible area in the editor window.
• Using "+" or "-" zooms in or out. Zooming center is the middle of the editor window.
• Using mouse wheel up or down you can scroll.
• Using "Ctrl" plus mouse wheel (up or down) zooms in or out.
• Using "Ctrl" plus holding the left mouse button, allows moving the visible area.
• "Undo" and "Redo" buttons are available only for the Diagram-Tab. Also the shortcuts "Ctrl+z" and "Ctrl+Z" can be used.
• In Entity-Declarations/Parameters-Tab, Architecture-Declarations/Internal-Declarations-Tab no "Undo" and "Redo" buttons
  are available, but shortcuts "Ctrl+z" and "Ctrl+Z" can be used.
• A "File" menu for reading and writing files and printing (encapsulated postscript) is available (shortcuts are available).
• A "HDL" menu for generating HDL and executing the compile-command is available (shortcuts are available).
• A search string entry field for the "Find"-Button is available (shortcut "Ctrl-f").
• A replace string entry field for the "Find & Replace"-Button is available (case insensitive).
  Find & Replace is done in Diagram-Tab, Entity-Declarations/Parameters-Tab, Architecture-Declarations/Internal-Declarations-Tab.
  Be aware that at signal names not the shown string in the schematic is changed by a Replace, but the underlying declaration.

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Generated HDL-Tab:

Here the generated HDL files are displayed for reading.

• Each generation replaces the old code with the new code.
• The generated HDL can be loaded into an editor by "Ctrl-e".
• When a code line is linked to the schematic, then the code line will be underlined, when the mouse pointer is at it.
• To follow the link the user must press the left mouse button together with the Ctrl-key.
• The schematic element which represents the code line will then be shown and highlighted.

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Compile Messages Tab:

The STDOUT and STDERR messages of the compile command appear in this tab.

• The tab is only cleared when the button "Clear" is pressed.
• The messages can be loaded into an editor by "Ctrl-e".
• When a line is linked to the "Generated HDL-Tab" and to the schematic in the "Diagram-Tab", the line will be underlined, when the mouse pointer is at it.
• To follow the link to the "Diagram-Tab" the user must press the left mouse button together with the Ctrl-key.
• To follow the link to the "Generated HDL"-tab the user must press the left mouse button together with the Alt-key.
• Per default the links are based on the message format of the "GHDL" VHDL-Compiler or the "iverilog" Verilog-Compiler.
• The message format can be adapted by using the Button "Define Regex for Hyperlinks".

Adapting the regular expression for the links:

• Per default the links for VHDL are based on the messages of the GHDL-VHDL-Compiler which look like: "M:/test.vhd:59:5: < some error message >" .
• Per default the links for Verilog are based on the messages of the iverilog-VHDL-Compiler which look like: "M:/test.v:59: < some error message >" .
• For following the link, the file-name and the line-number must be extracted from this message.
• This is done by a regular expression which must enclose the complete line and defines 2 groups.
• One group contains the file-name, the other group contains the linenumber.
• Then, to get the file-name, the complete line is replaced by the group which contains the file-name.
• Then, to get the line-number, the complete line is replaced by the group which contains the line-number.
• In order to adapt the regular expression to another HDL compiler the button "Define Regex for Hyperlinks" must be pressed.
• Then a dialog pops up, where the regular expression for the complete line and the 2 groups can be entered.
• In the 2 additional fields the group for the file-name and the group for the line-number must be specified.
• For the test of a different regular expression please use https://regex101.com.
• A debug mode for the regular expression can be activated, which gives information at STDOUT.

Here you can find links to 7 designs which I have created.
All designs are created by HDL-SCHEM-Editor and HDL-FSM-Editor and most of the designs are based at VHDL (only for division also Verilog is available).
By the link you will find all the needed source-files for both tools and also the generated VHDL/Verilog-files.

1. Cordic module
2. multiplication module
3. Karatsuba multiplication module
4. division module
5. division module at signed numbers
6. SRT division module
7. square module

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1. The Cordic module "rotate":

• The module "rotation" can rotate vectors by a given angle (Cordic rotation mode) or to the x-axis (Cordic vectoring mode).

• The module "rotation" can be configured by generics which define the number of bits of all the operands and which define the latency of the module (in clock cycles).

• The module "rotation" can be used to calculate the sine or cosine of an angle.

• The module "rotation" can be used to convert cartesian coordinates into polar coordinates and vice versa.

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2. The multiplication module "multiply":

• The module "multiply" multiplies signed numbers.

• The module "multiply" can be configured by generics which define the number of bits of all the operands and which define the latency of the module (in clock cycles).

• The module "multiply" has an architecture "struct" which implements the classic written multiplication algorithm.

• The module "multiply" has an architecture "fpga" which uses the VHDL multiplication operator.

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3. The Karatsuba multiplication module "multiply_karatsuba":

• The module "multiply_karatsuba" multiplies signed numbers.

• The module "multiply_karatsuba" can be configured by generics which define the number of bits of all the operands.

• The module "multiply_karatsuba" has an architecture "struct" which implements the Karatsuba multiplication algorithm.

• The module "multiply_karatsuba" has an architecture "mul_operator" which uses the VHDL multiplication operator.

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4. The non restoring division module "division":

• The module "division" calculates quotient and remainder from signed dividend and signed divisor.

• The signs are removed before an unsigned division is executed and added afterwards.

• The module "division" is available as VHDL and as Verilog design.

• The module "division" can be configured by generics which define the number of bits of all the operands and which define the latency of the module (in clock cycles).

• The module "division" uses a non restoring division algorithm.

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5. The non restoring division module "division_signed":

• The module "division_signed" calculates quotient and remainder from signed dividend and signed divisor.

• In contrary to the module division the signs are not removed before the division is executed.

• This leads to a quotient which is not coded as binary number with the bit weights 0 or 1,
  but as a number with bit weights +1 or -1. After the division this number is converted into a binary number.

• After the conversion the quotient and the remainder are fixed in some cases.

• The module "division_signed" can be configured by generics which define the number of bits of all the operands and which define the latency of the module (in clock cycles).

• The module "division_signed" uses a non restoring division algorithm.

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6. The SRT division module "division_srt_radix2":

• The module "division_srt_radix2" calculates quotient and remainder from signed dividend and signed divisor.

• The module uses the SRT algorithm to make fast divisions possible even at operands which have a large number of bits.

• As a radix2 SRT algorithm is used the quotient is first not coded as binary number with the bit weights 0 or 1,
  but as a number with bit weights -1, 0 or -1. After the division this number is converted into a binary number.

• The module "division_srt_radix2" can be configured by generics which define the number of bits of all the operands and which define the latency of the module (in clock cycles).

---

7. The square module "square":

• The module "square" calculates the square from a signed operand.

• The module is faster and smaller than the multiply module.

• The module "square" can be configured by generics which define the number of bits of the operand and which define the latency of the module (in clock cycles).

License:

HDL-SCHEM-Editor
Copyright (c) 2024 Matthias Schweikart

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

Files:

Python3 source code:
Start the tool by "python3 hdl_schem_editor.py" or create an executable with "pyinstaller --onefile hdl_schem_editor.py":

• Download from this website: hdl-schem-editor.zip (Number of downloads = 253 )
• Download from GitHub: HDL-SCHEM-Editor-main.zip (Number of downloads = 63 ).
  
• Download from GitHub: HDL-SCHEM-Editor.tar.gz (Number of downloads = 59 ).
  
• See also GitHub project.

Executable for Windows 11 (Number of downloads = 233 ):

• hdl_schem_editor.exe

Executable for Linux (compiled with Linux-Mint) (Number of downloads = 310 ):

• hdl_schem_editor

Small example design:

• HDL-SCHEM-Editor-Example.zip

Win11 Compile-script for hierarchical designs (Usage: compile.bat <module-name> hdl_file_list_< module-name >.txt):

• compile.bat

Change log:

Version 4.2 (15.11.2024):

• The hierarchy sidebar now also shows the hierarchy of a VHDL instance based on the information given in the "Additional files" field of the instance.
• The hierarchy sidebar window of the diagram-tab is now hidden at program start.
• A double click at the toplevel module in the hierarchy tree now opens the schematic instead of the HDL file.
• A double click at a VHDL-module in the hierarchy sidebar window now opens the architecture instead of the entity.
• The hierarchy is now loaded into the hierarchy sidebar window even when no HDL can be shown in the "generated HDL"-tab.
• The grid in the schematic can now be hidden for the session by the right mouse menu.
• In VHDL-mode the vertical size of the sub-windows in "Entity Declarations"-tab and in "Architecture Declarations"-tab now
  can be adapted by moving the separating line.
• When any edit dialog of a module is open, now HDL-generation is not possible anymore.
• When a design was closed and had changes which were discarded and HDL-SCHEM-Editor was not stopped by closing this window (because other designs
  were still loaded), then at opening the closed module again, the discarded changes showed up. Fixed.
• In Verilog-mode the string "Undo/Redo: Ctrl-z/Ctrl-y/Z" was shown twice in the Parameters-tab and in the Internal-Declaration-Tab. Fixed.
• When the field "VHDL library for instance" of an VHDL instance was empty, sometimes "compile through hierarchy" did not work. Fixed
• When a wire was started in an already existing dot, the wire could not be finished. Fixed
• When moving a wire, sometimes the signal name was not moved accordingly. Fixed.
• The "Additional sources" field in a symbol property dialog can now only be used for HDL-designs (and not for HDL-SCHEM- or HDL-FSM-Editor designs anymore).
• The "Additional sources" field in a symbol property dialog is now not a comma-separated list in a single line anymore, but a return-separated list in an entry box.
• When a VHDL-generate-line not only ends with an priority comment, but also has an additional comment text after the priority comment,
  then now the priority comment is removed from the comment when HDL is generated (instead of leaving it there).
• The entity-name is now shown bold in the VHDL architecture declaration.

Version 4.1 (09.10.2024):

• The diagram-tab now has a new sidebar which shows the hierarchy of the complete design in a tree.
• The color of the schematic background can now be changed (by right mouse click at schematic).
• The color of symbols can now be changed by right mouse click at symbols.
• The color of blocks can now be changed by right mouse click at blocks.
• When the mouse pointer is over a symbol for at least a second, then a small symbol information window pops up.
• Refactoring of list_separation_check.
• A double mouse click at a symbol, whose window was iconified, did not lift the window. Fixed.
• When a submodule of an opened hierarchical design was updated by the user by reading in the file, the file was read twice. Fixed.
• Sometimes opening of a Verilog submodule in a hierarchical design caused an exception. Fixed.
• An error message was created, when a sub-module was changed and saved without HDL generation and at the instance of the symbol properties were updated. Fixed.

Version 4.0 (20.09.2024):

• The underlying grid for the placement of schematic elements is now drawn in the schematic.
• The open-modules buttons are moved from the diagram-tab to the bottom of the top-window, so that they are accessible from all tabs.
• The eps-file created by the "Print" menu entry is now created in the working-directory and not in the directory, where HDL-SCHEM-Editor was started.
• When in a VHDL HDL-SCHEM-Editor schematic the architecture of a hse-instance was switched by "Edit properties" and afterwards the instance was double-clicked,
  the wrong architecture-name was shown in the architecture-select-combobox of the submodule schematic window. Fixed.
• When in a VHDL HDL-SCHEM-Editor schematic design the architecture of a hse-instance was switched by "Edit properties" and the new architecture did not exist,
  an exception happened. Fixed.
• When in a VHDL HDL-SCHEM-Editor schematic design the architecture of a hse-instance was switched by "Edit properties" and the new architecture was already selected in the sub-module,
  and the sub-module had been modified, the database of the submodule got corrupted at the next save into file. Fixed.
• When in a VHDL HDL-SCHEM-Editor schematic design a hse-instance is double clicked now always the architecture defined by the instance is opened.

Version 3.6 (11.09.2024):

• When a HDL-FSM-Editor design with a port of type integer is instantiated as a symbol, then the range of the integer gets lost. Fixed.
• Resizing a symbol by picking an edge did sometimes not work due to small discrepancies during coordinate calculations. Fixed.
• When a symbol is moved, which is very small because of zoom, it might happen, that the connected wires are disconnected from the symbol. Fixed.
• When 2 blocks have the same pseudo-comment for the order in HDL, now at generating HDL only 1 instead of 2 warnings pop up.
• Dots, which connect bus lines, are now displayed bigger.

Version 3.5 (31.07.2024):

• If a HDL-SCHEM-Editor module has comments at the the end of a signal-declaration and the signal is a port,
  then the module cannot be instantiated in another HDL-SCHEM-Editor schematic without loosing some other ports. Fixed.
• An initialization of a VHDL-port which has a range definition like "range 0 to 7" caused loosing this range at any instance of the module. Fixed.
• When a signal declaration is shown by the mouse pointer staying over the wire for some time, the declaration could sometimes stay visible after the wire was deleted. Fixed.
• When a string shall be replaced by using "Find & Replace" and the new string starts with the old string, then HDL-SCHEM-Editor runs into an endless loop. Fixed.
• Now a warning is shown, when a keyboard shortcut is used with a capital letter, but the shortcut is only defined for a lowercase letter.
• Messages in green color in the "Messages"-tab do not change their color into red anymore, when the mouse pointer is at such a message.
• When a signal name is edited, the cursor is now positioned at the start of the signal declaration and not at the end anymore.
• The entry "Hide ranges" or "Show ranges" is now visible again in the instance actions menue.
• When the mouse pointer is over a signal name for a short time, the upshowing box with the signal declaration now is always visible above all other items.

Version 3.4 (26.06.2024):

• The link to the source code from the Messages-Tab now also works for HDL-files which are not generated by HDL-SCHEM-Editor but are read at compile time.
  For opening these files the "editor command" defined in the Control-Tab, expanded by the option "-n<line-number>", is used.
• The last generic-definition in VHDL-mode may now end with a ';'.
• The last parameter-definition in Verilog-mode may now end with ','.
• HDL-SCHEM-Editor now gives the time the simulation needed in the message "Finished user commands from Control-Tab after <time-value>".
• When an instance got a new port by update from source, then the datatype of the port was not shown when the mousepointer was over its name. Fixed.
• When a module has a port with an integer range and the port was the last port, then the range was forgotten at the instance of the module. Fixed.
• When all ports of a symbol are already connected to signal-wires and "add signal stubs" is started, an exception happens. Fixed.
• VHDL syntax highlighting sometimes might cause an exception, when during editing the code is incomplete or wrong. Fixed.
• When a window is closed, sometimes its open-module-button was not removed. Fixed.
• After reading in a file, the undo-button was active even before the first user action. Fixed.
• When HDL-SCHEM-Editor was closed by "Exit all windows" a reminder dialog window could pop up for an already closed window. Fixed.

Version 3.3 (14.06.2024):

• Copying only a signalname but not the corresponding wire caused a crash. Fixed.
• When following a link from HDL to graphic, the highlighting color was changed from grey to orange.
• When following a link from HDL to a block, the line could only be highlighted, if the block was not edited. Fixed.
• After editing a design, HDL lines which were not supposed to get a link, had one from the previous HDL. Fixed.
• When a design was loaded by Ctrl-o with the focus in a text field (i.e. "Entity Declarations/Packages") the HDL was not linked to the source after file read but first after HDL generate. Fixed.
• When a design was loaded by command line parameter the HDL was not linked to the source after file read but first after HDL generate. Fixed.
• When a block-edit was started by following a link from HDL to graphic, the highlighting in the block-edit-window was not removed by Button-1 click. Fixed.
• When a file was opened which was already open in another window, only this window was moved in the foreground instead of also reading the file. Fixed.
• The group identifiers from the regex dialog of the Messages-Tab are now also stored in the module file.

Version 3.2 (09.05.2024):

• Sometimes the fast navigation buttons did not work correctly. Fixed.
• In VHDL mode embedded configurations for instances inside a generate are now supported.
• Compiler messages in the Messages-Tab are now colored in red.
• Following a link from the Messages-Tab into a generic map will now select the corresponding line in the generic map.
• In Verilog mode now ports and wires can be of type "signed" or "unsigned".
• It is now possible to open 2 different designs which use the same module name but different file names.
• Open text edit fields are now zoomed in the same way as all other graphic elements.

Version 3.1 (29.04.2024):

• Hyperlinks from Generated-HDL-Tab and from Messages-Tab are now also supported for Verilog.
• The default regular expression for identifying compiler messages is improved.
• A modified regular expression for identifying compiler messages in the Messages-Tab is now stored at file save.
• In the dialog for defining the regular expression now a debug mode can be activated, which gives information at STDOUT when the mouse moves over the messages.
• Modules without any ports sometimes damaged generated HDL. Fixed.
• When a Verilog design was read in, always the default VHDL (instead the stored Verilog) compile command was inserted in the Control-Tab. Fixed.
• In Verilog mode copying of wires damaged signal definitions. Fixed.
• In Verilog mode changing a signal declaration damaged signal declarations with sub-ranges of other wires with the same signal name. Fixed.
• In Verilog mode when editing code by an external editor the file-name extension ".vhd" was used instead of ".v". Fixed.
• A Verilog generate can now have a label.

Version 3.0 (23.04.2024):

• Hyperlinks from the HDL-code in the Generated-HDL-Tab to the schematic in the Diagram-Tab are now supported (see tab "Functionality" for a description).
• Hyperlinks from compiler messages in Messages-Tab (created by GHDL-VHDL-Compiler) to the schematic in the Diagram-Tab or to
  the Generated-HDL-Tab are now supported (see tab "Functionality" for a description).
• Adapting the method for creating links from the Messages-Tab to other HDL-compilers is now supported by
  a dialog to modify the needed regular expression (see tab "Functionality" for a description).
• After a design change now first HDL must be generated before the compile command can successfully be started.
• When HDL is generated now all changed but not saved HDL-SCHEM-Editor designs are first automatically saved,
  to keep the content of the HDL consistent with the content of the hse-file.
• After a design change now first HDL must be generated before the compile command can successfully be started.
• When the mouse pointer is over a wire for at least 2 seconds, then now the signal declaration of the wire is shown.
• There is a new entry in the HDL menu: "Force Generate through hierarchy".
• When a VHDL module is instantiated, now port definition lists at the module in the "list" format (for example: "a, b, c : in std_logic;") are supported.
• When a design is loaded, now the HDL-tab is only filled with HDL, if the HDL is newer than the design file.
• If in a VHDL design an embedded configuration statement for a symbol was selected and the instance name of the symbol had a comment,
  this comment was wrongly placed in the middle of the embedded configuration statement and corrupted the VHDL. Fixed.
• If a recursive HDL design had a loop which involved more than 1 level of hierarchy, HDL generation through hierarchy run into an endless loop. Fixed.
• When a new window was opened the accelerator-keys did not work before a click into the window. Fixed.
• When "Redo" was used in some text fields and the Redo-stack was empty a TclError was thrown. Fixed.
• When switching architectures in a VHDL design, sometimes the HDL-tab was not updated accordingly. Fixed.

Version 2.7 (04.04.2024):

• HDL-Generation could connect a wrong signal to a port, if a signal name was identical to the end of another signal name. Fixed.
• When a wire end was moved with "Shift" pressed, the signal name sometimes moved in a wrong way. Fixed.
• When a HDL-SCHEM-Editor design was changed, reading from the source file to undo the changes did not work. Fixed.
• Undo sometimes skipped changes at symbols or generate frames. Fixed.
• At the end of moving a selection, the selection did sometimes not snap to grid. Fixed.
• Find&Replace now works also in generate conditions.
• HDL-SCHEM-Editor now supports alternative architectures for a VHDL design.
• Added new buttons at the bottom of the diagram tab for fast navigation between all opened modules (allows to keep all open designs in full screen mode).
• When the mouse pointer is over a port name for a second, the complete declaration of the port is now shown.
• When the mouse pointer is over a signal name for a second, now a white background for better readability is shown.
• A block and its text cannot hide other schematic elements anymore.
• A recursive instantiation (a module is instantiated in itsself) is now supported.

Version 2.6 (13.03.2024):

• The hierarchical HDL-generation of HDL-SCHEM-Editor now can generate HDL for a HDL-FSM-Editor submodule (if HDL-FSM-Editor 3.10 or newer is used).
• Wire highlighting by right mouse button is now implemented.
• If a straight wire has one open end and the other end is connected to a symbol, then moving the symbol now always moves the signal name.

Version 2.5 (07.03.2024):

• When an input or output had an initialize value the generated VHDL was corrupted. Fixed.
• Copying into another schematic-editor-window now also works when this window has another zoom factor than the original window.
• All buttons of the diagram-tab are now placed at the left side instead of the bottom side to fit better at small displays.
• Added the message "HDL generation ready" for generating HDL through hierarchy.
• The checking of the command line parameters is now done by ArgParse.
• The window title was changed so that the module-name now can always been read at the icon in the taskbar.
• A comment at the end of an instance name is now not shown anymore in the symbol property window.
• A ';' at the end of a word is now not selected anymore by a doubleclick at the word.
• The new commandline switch -no_message was introduced to prevent HDL-SCHEM-Editor from printing a message at start.

Version 2.4 (01.02.2024):

• Due to a bug HDL generation for a single module did not work anymore (through hierarchy did work). Fixed.

Version 2.3 (31.01.2024):

• At block movements sometimes signal names were moved wrongly. Fixed.
• When a HDL-SCHEM-Editor project file of a submodule not exists, then an empty error message was generated. Fixed.
• When HDL-generation failed, sometimes a message in the Messages-Tab was shown, which said "HDL was generated". Fixed.

Version 2.2 (26.01.2024):

• Find&Replace did only replace the first occurance of a search string in the Entity/Architecture/Parameters/Internal Declaration tab. Fixed.
• At block edits sometimes additional blanks were added at line ends. Fixed.
• When the text of a block was not completely included in the surrounding "generate" rectangle, the text was not put into the generate loop of the HDL. Fixed
• When the text of a block exceeds the block-rectangle and overlaps some other items, it does not prevent actions on these other objects anymore.
• When HDL-SCHEM-Editor automatically adds a signal stub to a port of an integer type with range, the range is now also added to the signal.
• Scrolling by mousewheel did not work under Linux. Fixed.
• When a wire is disconnected and moved with "shift", its signal name now always stays at the grid.
• Fixed documentation: Search is case insensitive since version 1.8 .
• Now a file containing the VHDL architecture of an instance can additionally be added as source code in the instance properties dialog.
• The module-name is now shown in all error-messages.
• The working directory (configured in the control-tab) is now printed in the message tab at any compile.
• If a text field has more than 100000 characters, then syntax highlighting is deactivated, because it takes too much time.
• During a search started by "Find" no new search can be started by the "Find" button.
• HDL-SCHEM-Editor now does not ignore the default hierarchical compile command anymore.
• Generate frames are now exactly placed onto the grid.
• The "Paste"-button now only gets active, when the selection was not empty.
• The "Paste"-button now stays active after "Paste", because the copy buffer can be pasted again.
• The windows style Control-y for Undo-operations is now supported correctly.
• When the external editor is not found by an edit-action, now in all cases the error-message pops up correctly.
• "View all" at very large schematics now works even if the fontsize was calculated to be 0.
• Connectors are now always drawn in the background to make not correct connected wires visible.
• Wires which did end in a symbol, but not at a connection point, did behave as if they were connected. Fixed.

Version 2.1 (31.12.2023):

• "Wait" from VHDL is now syntax highlighted.
• When a design is already open in a window it cannot be opened anymore in another new window.
• In the control tab now file-names containing blanks can be quoted by " or '.
• There was a crash when creating HDL from a schematic which has a VHDL instance. Fixed.
• Changes in Interface/Internals-tabs by external editor were first recognized for HDL generation after pressing a key in that fields. Fixed.
• At paste by the paste-button two mouse-clicks were needed to move the new objects. Fixed
• At copy/paste the new objects sometimes were not placed exactly at the grid. Fixed
• At instantiating a module the range of a port with type integer/natural was ignored. Fixed
• Moving symbol ports sometimes did not move the connected wire. Fixed
• The messages tab does not show empty lines anymore.

Version 2.0 (01.12.2023):

• At opening a design, sometimes the rectangles around blocks increased their size unexpectedly. Fixed.
• As now all known small bugs are eliminated, it is time to increase the version number to 2.

Version 1.10 (29.11.2023):

• At "generate through hierarchy" now HDL is also generated for all changed but not saved modules.
• When the generic map is edited, edit windowe will now not shrink under the size it had at start of edit.
• Picking up the endpoint of a line (by mouse-pointer) is now easier.
• Syntax highlighting now also works in VHDL functions and procedures.
• Using compile-commands and external editor command did not work properly under Linux. Fixed.
• Small movements of instances sometimes moved the symbol away from the grid (introduced in version 1.9 by the fix regarding double clicks). Fixed.
• When declarations where edited by an external editor, then afterwards syntax highlighting did not work until a first key stroke. Fixed
• An update of the filename of a symbol did unnecessarily cause 2 entries at the undo-stack. Fixed
• When a hdl-file-list is created (by compiling through hierarchy), then the path to a HDL-file of a symbol, which was generated by HDL-FSM-Editor,
  is now fetched from the HDL-FSM-Editor hfe-file and not from the symbol anymore.
  This helps in case the user forgot to update the symbol after the generate path for HDL was changed in the hfe-file.

Version 1.9 (23.11.2023):

• At HDL generation empty fields are now also detected by checking with "isspace".
• Moving a generate-frame by picking the condition now also places the generate-frame onto the grid.
• There is now an error message when the user tries to compile the design, but no compile command is specified.
• Arrays of arrays are now supported as wire types.
• A working directory for the compile commands can now be specified in the control tab.
• Undo/Redo now works also in generic maps.
• A double click at a symbol (in order to open it) sometimes signaled a design change by adding a '*' to the filename. Fixed.
• After reading a design sometimes scrolling or "view all" was needed to move the schematic into the window. Fixed.
• Signal names sometimes could not be moved exactly at a wire. Fixed.
• Several instances of the same module had all always the same generic map in HDL. Fixed.
• When a block was edited and the block was deleted during edit, then the edit-window was not deleted. Fixed.
• When a module was instantiated several times, then the hdl-file-list contained the module (and its hierarchy) also several times. Fixed.
• After copy/paste signal names could not be moved anymore to the grid. Fixed.
• When a new design was loaded (by "open") the undo stack was not cleared. Fixed.
• When a block was edited, "redo" did not work. Fixed.

Version 1.8 (09.11.2023):

• Aborting a file opening caused a crash. Fixed.
• Syntax highlighting during editing of a block did not work correctly. Fixed.
• The "new instance" button stayed pressed after its first use under Linux. Fixed.
  
• The shortcut "control-e" now also works under Linux.
• Copy/Paste into another window is working now.
• Search is now case insensitive.
• Arrows to wires are now added with the right mouse button (Alt-Button1 did not work under Linux).
• The Messages-tab has now a clear button.
• When signal stubs are added, then now wire-dots are added.
• When signal stubs are added, the signal names are not placed at half of the underlying grid distance anymore.
• Wires which have the VHDL signal types integer/natural are now shown as bus.
• At opening of a new file, all still open editing actions (edit of block, signal-name, instance-name, generic-map) are
  aborted now, before the new design is loaded.
• "Exit all windows" now reports unsaved changes and asks for dismiss before closing the window.
• The shortcut "control-o" does not insert a new line in the text area, where it is used.
• In a VHDL design the statements "library ieee; use ieee.std_logic_1164.all;" are now automatically filled in the "Packages" field of the "Entity Declarations"-tab.
• The complete signal type is now showed when mouse is over wire.

Version 1.7 (23.10.2023):

• When working with hierachical HDL-SCHEM-Editor schematics, defining unambiguous IDs for the graphical elements got confused.
  This caused problems at many actions initiated by the user. Fixed.
• Wires could sometimes only be moved in unexpected manner because of inaccurate coordinates after zooming. Fixed.
• After moving a selection the moved elements are not de-selected anymore, but stay selected.
• Signal names can now not be positioned at half of the grid-distance anymore.
• Signal names are now more intuitive moved, when a wire is moved.
• The size of the dots, which connecting wires, are now adapted at zoom.
• When comparing coordinates of schematic elements for equality now their difference is compared to a limit,
  in order to avoid graphical problems caused by inaccuracy.

Version 1.6 (19.10.2023):

• After deleting an single element of the schematic by the delete key, drawing a selection was not possible until another element was entered. Fixed.
• Opening a new window by using the shortcut "Control-n" did not work anymore. Fixed.
• Editing a signal name sometimes caused an exception. Fixed.
• Moving a symbol with a connected wire beyond the next edge of the wire caused "diagonal" wires. Fixed.
• Dots which connect wires, sometimes were moved in a wrong way. Fixed.
• Using integer-comments for the order of schematic elements in a Verilog design had some problems. Fixed.
• At a replace-action now the complete signal declaration can be modified and not only the visible part of the signal declaration.
• The entry fields of the Control-Tab now have the same size as the window.
• When the HDL of a sub-module is generated by "Generate through hierarchy" and the sub-module design file is already openend in HDL-SCHEM-Editor,
  then the HDL-tab of the sub-module is now updated.
• Port names of components and instances are now sorted alphabetically in HDL.
• Integer parameters of Verilog-modules instantiated into a VHDL design are now correctly translated into
  a VHDL generic-map/generic-definition (may not be supported by VHDL tool chains).

Version 1.5 (13.10.2023):

• Added documentation for the button "New Generate". Functionality was already added in 1.4
• Added documentation for the field "Additional sources" of the Control-Tab. Functionality was already added in 1.4
• Generate HDL through hierarchy destroyed the accellerator-key-bindings of the schematic-window-menus. Fixed.

Version 1.4 (12.10.2023):

• Added documentation for the Control-Tab: Description of HDL-FSM-Editor-command was missing.
• Added syntax highlighting for VHDL assertions.
• When a text is edited in an external editor but is not changed, then this is not handled as a design change anymore.
• At the end of a string search by the Find-Button now "end of file" is signaled.
• The "update symbol from source"-entry of the instance action menu is now split into 2 entries
  named "update symbol from source (with generics)" and "update symbol from source (without generics)".

Version 1.3 (27.09.2023):

• When a text was edited using the external editor command, then at copying back the text into the design, all tabs will be replaced by four blanks.
• When a new window is opened now the key-shortcuts (for example "Control-o") are mapped to the new window without any mouseclick into it.
• When a symbol is updated by its source file, now also the module name gets updated.
• Find/Replace now also works for "Generics", "Architecture First Declarations" and "Architecture Last Declarations".
• Find/Replace can now not only be "undone" in the Diagram-Tab,
  but also in the Entity-Declarations/Parameters-, Architecture-Declarations/Internal-Declarations-Tab.
• Text elements which are not changed by Find/Replace do not cause an entry in the undo/redo stack anymore.

Version 1.2 (22.09.2023):

• The file menu now has 2 exit entries: "Exit Window" and "Exit all windows".
• The "find & replace" feature is implemented.
• If the schematic of a symbol was already opened by a double click, a next double click does not open
  a new window anymore, but moves the already open window in the forground.
• When a symbol of a hdl-schem-editor instance is doubleclicked, sometimes the new window does not get the focus. Fixed.
• When ports with connected wires are moved, the automatic wire dot insertion did not work. Fixed.
• After working with a selection sometimes the window focus gets lost. Fixed.
• A sub-design could not be opened anymore after hierarchical HDL generate. Fixed.
• Fixed bug regarding sub slices when Verilog wire is connected to another wire by changing its name.

Version 1.1 (17.09.2023):

• Removed the old and obsolete file hdl-schem-editor.py from the zip-archive (hdl_schem_editor.py is the file to be used).
• A declaration of a VHDL-constant is now detected by VHDL syntax highlighting.
• In the control-tab now all entry-fields have the same width.

Version 1.0 (11.09.2023):

• Initial version

If you detect any bugs or have any questions,
please send a mail to "matthias.schweikart@gmx.de".
Bug fixing will be done fast, feature wishes will be seriously considered.

The download curves are linear interpolated from 2022-09-25 to 2024-09-24, as during this time the download-numbers were not observed.