HDL-SCHEM-Editor for VHDL and Verilog

(See also HDL-FSM-Editor for VHDL and Verilog)

HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design

Features:

Advantages:

Prerequisites:

Commandline parameters:


Control-Tab:

Here you define several items which control the generation of the HDL-design:


Entity-declarations-Tab (VHDL) / Parameters-Tab (Verilog):


Architecture-Declarations-Tab (VHDL)/Internal Declarations-Tab (Verilog):


Diagram-Tab:

The schematic is drawn in this tab and a hidable hierarchical view is available (from which designs can be opened by doubleclick).
Each graphical element can be moved by picking it with the left mouse button.
Each graphical element can be deleted by moving the mouse pointer over the element and pressing the "Delete" key.
For VHDL designs several alternative schematics can be entered by using the "new Architecture" button (which architecture is used is controlled by the instance).
The following graphical elements are available:

Configure and manipulate the graphical elements:

Editing actions:


Generated HDL-Tab:

Here the generated HDL files are displayed for reading.


Compile Messages Tab:

The STDOUT and STDERR messages of the compile command appear in this tab.

Adapting the regular expression for the links:

HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design HDL-SCHEM-Editor window showing an example design

Here you can find links to 7 designs which I have created.
All designs are created by HDL-SCHEM-Editor and HDL-FSM-Editor and most of the designs are based at VHDL (only for division also Verilog is available).
By the link you will find all the needed source-files for both tools and also the generated VHDL/Verilog-files.

  1. Cordic module
  2. multiplication module
  3. Karatsuba multiplication module
  4. division module
  5. division module at signed numbers
  6. SRT division module
  7. square module


1. The Cordic module "rotate":


2. The multiplication module "multiply":


3. The Karatsuba multiplication module "multiply_karatsuba":


4. The non restoring division module "division":


5. The non restoring division module "division_signed":


6. The SRT division module "division_srt_radix2":


7. The square module "square":

License:

HDL-SCHEM-Editor
Copyright (c) 2024 Matthias Schweikart

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

Files:

Python3 source code:
Start the tool by "python3 hdl_schem_editor.py" or create an executable with "pyinstaller --onefile hdl_schem_editor.py":

Executable for Windows 11 (Number of downloads = 233 ):

Executable for Linux (compiled with Linux-Mint) (Number of downloads = 310 ):

Small example design:

Win11 Compile-script for hierarchical designs (Usage: compile.bat <module-name> hdl_file_list_< module-name >.txt):

Change log:

Version 4.2 (15.11.2024):

Version 4.1 (09.10.2024):

Version 4.0 (20.09.2024):

Version 3.6 (11.09.2024):

Version 3.5 (31.07.2024):

Version 3.4 (26.06.2024):

Version 3.3 (14.06.2024):

Version 3.2 (09.05.2024):

Version 3.1 (29.04.2024):

Version 3.0 (23.04.2024):

Version 2.7 (04.04.2024):

Version 2.6 (13.03.2024):

Version 2.5 (07.03.2024):

Version 2.4 (01.02.2024):

Version 2.3 (31.01.2024):

Version 2.2 (26.01.2024):

Version 2.1 (31.12.2023):

Version 2.0 (01.12.2023):

Version 1.10 (29.11.2023):

Version 1.9 (23.11.2023):

Version 1.8 (09.11.2023):

Version 1.7 (23.10.2023):

Version 1.6 (19.10.2023):

Version 1.5 (13.10.2023):

Version 1.4 (12.10.2023):

Version 1.3 (27.09.2023):

Version 1.2 (22.09.2023):

Version 1.1 (17.09.2023):

Version 1.0 (11.09.2023):

If you detect any bugs or have any questions,
please send a mail to "matthias.schweikart@gmx.de".
Bug fixing will be done fast, feature wishes will be seriously considered.

The download curves are linear interpolated from 2022-09-25 to 2024-09-24, as during this time the download-numbers were not observed.

hfe_hse designs